Chiplets: The Future of Semiconductor Design with Steven Slater

I say opportunities that having a chiplet kind of architecture puts out there is this concept of maybe, you know, there's one functional block that's working really well at a, you know, not cutting edge technology. Maybe it's like, you know, 13 nanometer or something like that. And it works quite, it works perfectly well. We've got, you know, great confidence in its reliability.

And as long as it has a standardized kind of IO, you know, interface, then we'd have the ability to put that together in the same package as another chiplet that's on the absolute latest cutting edge process node. I'm just making sure that we spend time looking at the interconnect and making sure that the interconnects are going to work. Music.

Hi, everyone. It's Judy Warner. Welcome back to this week's ecosystem podcast. Today, we're going to be talking all about chiplets. I've asked my friend Steven Slater, who is the Director of Product Management at Keysight, to come on and talk to you about everything that's going on in the industry with chiplet technology. We talk about the UCIE Consortium and how that's coming along, the ecosystem that is enabling the technology. We talk about who needs it and why, who's being successful at it,

and we're going to give you some deep insights from his insider view. you. If you enjoy this podcast, Keysight is also doing a webinar that will go deeper into a simulation software that they offer as part of a ecosystem solution. I put that and several other places you can plug into the ecosystem for chiplets below. Without further ado, let's jump into our conversation with Stephen Slater of Keysight EDA.

Hi, Stephen. Thanks so much for joining us today. It's been a while and I look forward to catching up with you and talking a a little bit about chiplets today. Yeah, it's always great to catch up with you. I think the last time we met was at DesignCon. Yeah, it was. And it seemed like a brief meeting too, because we were all running around like crazy. So eager to catch up. I know you're a busy guy.

Well, today I wanted to talk to you about chiplets. And I know that's something you've had your hands on for a little while. And I'm sure the audience wants to learn more about where we are with chiplets.

So we've been talking about chiplets, it seems like, for I don't know a few years at least in my estimation maybe longer but like where are we can you tell us like where we are as far as adoption goes across the industry yeah I think for for us we were we were very big into uh hbm simulating hbm and and you know it was like silicon interconnects between that and uh and another die and that was kind of our first kind of interest area into that space

But probably about two years ago at our design con, all of a sudden, that's what everybody was talking about was, hey, this is really going to be part of the future. And I think it was mostly, you know, all of the big players, the types of customers like, you know, Intel and AMD, who were already having successful kind of designs that were making use of chiplets. That was the way that they were getting to the size and scale and yield that they required.

And, you know, everyone was really interested. And probably, you know, in the last year, there's been a ton of development and progress, and especially with things like the UCIE standard. So universal chiplet interconnect, that came to fruition and helped to ensure that they can build a chiplet ecosystem for the future.

Right. So who needs this technology and why do they need it and who's adopting this technology since you've been up close to some of the UCIE standards and information? What are you seeing? Yeah. So I think it's important to note, you know, think about who's successful with it today.

And, you know, a lot of the drivers for needing to go to a chiplet, you know, type of architecture was because the individual dyes themselves were getting so big that you ended up getting really poor yield out of a given wafer. So they decided that if they could actually break them down into small functional blocks, therefore you're throwing away much fewer parts of the wafer.

So you get this higher yield and yet you could still get great performance because you can put them together and make sure that they're connecting with very high speed interconnects. In doing so, you actually get to then get past the total radical limit of a given technology. So you can start to build these really giant processes as would be needed for things like AI engines that go into data centers. So those type of companies are very successful already.

Already, and there's certain foundries out there, such as TSMC, that have been putting in place a most definite series of processes to enable these chipless to be produced, to be packaged together, and yeah, there's a lot of things that need to line up in order to make this a success, but that looks to be the future.

So that's part of the question, who's successful today? day but you know your real question is who needs this and i was really surprised actually that it really touches upon many different industries so the types of you know customers who are interested those who have joined the the ucie consortium come from all manner of like aerospace defense and then also you know those from automotive space as well and you know what i here is that these companies are interested in pursuing

chiplets because it gives them better reuse inside their own company so they'd be developing chiplets that would then be reused on evolutions of products so inside their own company and then also them thinking about new business models to be able to sell that particular functional block that they do a really good job at that's there, competitive differentiator, and being able to sell that on an open chiplet ecosystem market.

I think that's really exciting for everybody. So that's what Keysight would really like to hope to enable.

So, when they put these chiplets together, these functional blocks that you talked about, are they put together in scale, like you said, that can be reused, or are they highly customized for specific applications? Yeah, so the individual blocks, it can be a little bit of both, right? Right. So I think one of the key points about it would be that as you progress to lower and lower process nodes, not every part of the IC scales down accordingly.

So there's, and in doing so, I'm trying to scale something down. Then there's a lot of re-verification work that needs to happen to make sure that the circuit still works.

Works so kind of the one of the interesting i say opportunities that having a chiplet kind of architecture puts out there is this concept of maybe you know this one functional block that's working really well at a you know not cutting edge technology maybe it's like you know 13 nanometer something like that and it works quite it works perfectly well we've got you know great confidence in its reliability.

And as long as it has a standardized kind of IO interface, then we'd have the ability to put that together in the same package as another chiplet that's on the absolute latest cutting edge process node. I'm just making sure that we spend time looking at the interconnect and making sure that the interconnects are going to work with best signal integrity.

And so sort of as an adjunct to that question, since we're talking to engineers here, right, what are you seeing as far as the enablers of the technology, which is some of what you just talked about, but what are also some of the roadblocks maybe? And maybe you can speak to sort of where we're going with those enablers and roadblocks as you see it. Yeah, for me, the enablers have to be, you know, the collaborations and in a kind of like open, you know, sharing of standards, things like this.

So what I do see out there is I see some convergence in, for instance, the IO. So it seems like UCIE is really taking off. There's a lot of companies that are, again, part of that consortium. A lot of papers that get produced now, they're talking about UCIE.

I would also like to call out companies like AlphaWave that have created UCI-E PHY IP that you can just take and drop into your IC, and they've actually taped it out, and they simulated with our toolset to make sure before they got there that even at the advanced packaging, the UCI-E advanced high-speed interconnect, that they were able to get good signal integrity, and then taped it out and verified. And so, you know, that FIIP is for sure a big enabler of, you know, this ecosystem.

But it's more than that, because you have to look at then to the things like the foundries and their own introduction of certain standards for how you send all your data files, because this now is about kind of three dimensional structures and how they're going to be connected. And so they've come up with their own, TSMC came up with 3D blocks specification, and there's many EDA companies that are participating to help define it and take it forward.

But these are the right types of things that need to happen in order for many, many more companies to be able to play in this chiplet ecosystem. Yeah. If you were looking at a scale of zero, we have no chiplets to five, we can scale.

Where are we? Would you say one to five? I still think we're in the early stages, maybe two along the path. That's great because last year I probably would have said one. But I'm basing that just upon the amount of interest that we see and the amount of customers that are talking to us about trying to simulate things like UCIE.

You know uh some of the challenges i think i missed that from your earlier question what some of the challenges or barriers are still out there of course when you introduce new packaging technologies like this is always going to be those certain technical aspects that need to be they need to be figured out so for instance everything's going to be connected now in a package but you know what about thermal you know what about uh vibrational mechanical stress you know these are items which somehow

need to be kind of co-optimized with the the design or at least like the floor planning of where you're going to put the individual functional blocks, so there's always going to be a trade-off between things like you know the signal integrity you could have perfect signal integrity by making sure that the critical nets are really really close together and making sure you don't have excessive crosstalk but you're going to have to be a little careful because of things like thermal considerations.

I'd love to mention power as well. I think power is going to be very, very interesting because each of these individual, you know, chiplets needs to be powered up, but that means you have to be very careful thinking about the power distribution network as you come up through the package and then, you know, up into the individual chiplets. And I think that's going to become a bigger challenge for people to simulate and verify before they go and build power.

Well, you had mentioned when you were discussing AlphaWave the necessary piece of simulation, which, of course, is your wheelhouse.

What does the simulation landscape look like right now? Is that something you're developing? It sounds like you're working with the UCIE consortium. And how are people going to simulate this early in the game and as they move forward?

Word yeah absolutely yeah so i think we're in a very very very favorable position at the moment we came first to market with a simulation analysis flow for ucie so it's a it's a signal integrity you know looking at how how open the eyes will be under various considerations those those eyes and how they open up you need a you need to correct settings per the standard for the transmitter and good models for the transmitter you need models for the channel i need models for the receiver,

and not only that there's a few special things in the standards such as this is like for kind of compliance that they call like a voltage transfer function and another one which is you know a quad data rate clocking which so it's qdr that's something that would be needed for the the really faster speeds of of ucie and you know very thankfully we built this simulation solution we We called it Chiplet Fire Designer, but it's a part of Advanced Design System, ADS, which many of you viewers will

probably be aware of. Yeah, of course. Well, I know that I only have you for a few short moments. This is, you know, talking to engineers.

What would you recommend or where would you recommend they go to learn more, say, about Chiplet 5, but also just learn or getting involved in the consortium or just getting up to speed on Chiplet technology and trying to figure out if it's a direction they should go? Yeah, absolutely.

Yeah, I definitely think, you know, a lot of the big shows out there, such as DAC, Design automation conference as well as things like the chiplet summits that happen and they happen in various locations i think those are great places to be attending to try to hear the the latest i definitely know that uh for the ecie consortium they they have you know good uh like working group meetings finally i would say that if you want you know if what you heard today

sounds kind of interesting from the simulation perspective then we do have a webinar coming up and this webinar And I was going to be actually showing the simulation solution, this chiplet fire designer. So I believe it's a couple of dates for Americas and Europe, but it's coming up later in July. So, you know, please look out for that. And maybe Judy might have a link that we could post. Yeah, I'll make sure that I get that from you and your team.

So thanks for that. And the other recommendations as well.

Stephen, thank you again for giving us the short treatment on chiplets.

I think it's very interesting. interesting and my last question is you are you seeing a lot of chiplet papers pop up at say design con and DAC and some of these shows yeah definitely a marked increase and and for instance in things like I would say a DAC a lot of the poster sessions talking a lot about you know floor planning and placement and you know trying to optimize you know for for you know a better overall performance and not to mention it's probably a topic for another day

but you know The rise of AI inside of EDA tools. And I think that's another very, very interesting kind of direction that the industry is taking. Yeah, absolutely. It seems like it's everywhere at all times and all platforms. So, well, Stephen, thank you again for coming on and giving us at least a brief overview of where the industry is at with chiplets. I will definitely share the Keysight webinar and some of those other links you shared with me.

Thanks again, and come back soon. We'll geek out about AI and EDA tools later. That sounds like a good topic as well. Absolutely. Thanks so much, Judy. I appreciate it. Thank you for everyone for watching. Thanks for everyone for joining today. I hope you enjoyed this conversation with Stephen Slater of Keysight. We'll see you next week. Until then, remember to always stay connected to the ecosystem. Music.